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Espressif Systems /ESP32-C2 /SPI0 /CACHE_FCTRL

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Interpret as CACHE_FCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CACHE_REQ_EN)CACHE_REQ_EN 0 (CACHE_USR_ADDR_4BYTE)CACHE_USR_ADDR_4BYTE 0 (CACHE_FLASH_USR_CMD)CACHE_FLASH_USR_CMD 0 (FDIN_DUAL)FDIN_DUAL 0 (FDOUT_DUAL)FDOUT_DUAL 0 (FADDR_DUAL)FADDR_DUAL 0 (FDIN_QUAD)FDIN_QUAD 0 (FDOUT_QUAD)FDOUT_QUAD 0 (FADDR_QUAD)FADDR_QUAD

Description

SPI0 bit mode control register.

Fields

CACHE_REQ_EN

For SPI0, Cache access enable, 1: enable, 0:disable.
CACHE_USR_ADDR_4BYTE

For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
CACHE_FLASH_USR_CMD

For SPI0, cache read flash for user define command, 1: enable, 0:disable.
FDIN_DUAL

For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
FDOUT_DUAL

For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
FADDR_DUAL

For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
FDIN_QUAD

For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
FDOUT_QUAD

For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
FADDR_QUAD

For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data